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ISL3873A Datasheet(PDF) 19 Page - Intersil Corporation

Part No. ISL3873A
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873A Datasheet(HTML) 19 Page - Intersil Corporation

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19
DQPSK, or CCK. The preamble is used by the receiver to
achieve initial Pseudo Noise (PN) synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer link.
The transmitter generates the synchronization preamble and
header and knows when to make the DBPSK to DQPSK or
CCK switchover, as required.
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,
it uses four of those bits to select one of 16 complex spread
sequences from a table of CCK sequences. Thus, there are
16 possible spread sequences to send, but only one is sent.
This sequence is then modulated on the I and Q outputs.
The initial phase reference for the data portion of the packet
is the phase of the last bit of the header. At 11Mbps, one
byte is used as above where 8 bits are used to select one of
256 spread sequences for a symbol.
Bit rates for the ISL3873A are defined in Table 6. This table
provides information on bit rates, data rates and symbol
rates for an MCLK of 44MHz clock. Figure 13 shows the
modulation schemes for the different bits rates. The
modulator is completely independent from the demodulator,
allowing the PRISM baseband processor to be used in full
duplex operation.
Header/Packet Description
The ISL3873A is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions. The
ISL3873A generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE 802.11-1997 1 and 2Mbps modes and the
second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy
equipment.
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1’s
(before entering the scrambler) plus a Start Frame Delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192
µs.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at the
2Mbps rate. The synchronization preamble is all 0’s to
distinguish it from the long header mode and the short
preamble SFD is the time reverse of the long preamble SFD.
The duration of the short preamble and header is 96
µs.
Start Frame Delimiter (SFD) Field (16 Bits)
This field is used to establish the link frame timing. The
ISL3873A will not declare a valid data packet, even if it PN
acquires, unless it detects the SFD. The ISL3873A receiver
auto-detects if the packet is long or short preamble and sets
SFD time-out. The timer starts counting after initialization of
the de-scrambler is complete.
RX_RF_AGC
RX_IF_DET
THRESH.
IF
DAC
I ADC
Q ADC
RX_Q
±
RX_I
±
RX_IF_AGC
HFA3683
HFA3783
ISL3873A
6
6
7
1
1
I/O
DEMOD
AGC
DATA I/O
DETECT
CTL
FIGURE 12. AGC CIRCUIT
TABLE 6. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE
(Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
ISL3873A


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