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ISL3873A Datasheet(PDF) 16 Page - Intersil Corporation

Part No. ISL3873A
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873A Datasheet(HTML) 16 Page - Intersil Corporation

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PE1 and PE2 encoding details are found in Table 2.
Note that during normal receive and transmit operation that
PE1 is static and PE2 toggles for receive and transmit
states.
Master Clock
Prescaler
The ISL3873A contains a clock prescaler to provide flexibility in
the choice of clock input frequencies. For 11Mb/s operation, the
internal master clock, MCLK, must be at least 11MHz. The
clock generator itself requires an input from the prescaler that is
twice the desired MCLK frequency. Thus the lowest oscillator
frequency that can be used for an 11MHz MCLK is 22MHz. The
prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5).
Another way to look at it is that the divisor ratio between the
external clock source and the internal MCLK may be integers
between 2 and 14.
Typically, the 44MHz baseband clock is used as the input, and
the prescaler is set to divide by 2. Contact the factory for further
details on setting the clock prescaler register in the ISL3873A.
Low-Frequency Crystal
The ISL3873A MAC controller can accept the same clock signal
as the PHY baseband processor (typically 44MHz), thereby
avoiding the need for a separate, MAC-specific oscillator. The
ISL3873A input has a low-frequency oscillator. This low-
frequency oscillator is intended for use with a 32.768KHz,
tuning-fork type watch crystal to permit accurate timekeeping
with very low power consumption during sleep state.
If a 32.768KHz crystal is connected, the resulting LF clock is
supplied to an interval timer to permit measuring sleep
intervals as well as providing a programmable wake-up time.
In addition, the clock generator can operate either from CLKIN
or (very slowly) from the LF clock. Glitch-free switching
between these two clock sources, under firmware control, is
provided by two, non-architectural Strobe functions (“FAST”
and “SLOW”). In addition, during hardware reset, the clock
generator source is set to the LF clock if no edges are
detected on CLKIN for two cycles of the LF clock (roughly 61
microseconds). This allows proper initialization with omission
of either clock source, since without the LF crystal attached
there will not be cycles of the LF clock to activate the detection
circuit. The ability to initialize the ISL3873A using the LF
oscillator to generate MCLK allows the high-frequency (PHY)
oscillator to be powered down during sleep state. If this is
done, firmware can turn on power to the PHY oscillator upon
wake-up, and use the interval timer to measure the start-up
and stabilization period before switching to use CLKIN.
Clock Generator
The ISL3873A can operate with MCLK frequencies up to at
least 12MHz and CLKIN frequencies of at least 50MHz. The
MCLK prescaler generates MCLK (and QCLK) from the
external clock provided at the CLKIN input, or from the output of
the LF oscillator. The MCLK prescaler divides the selected
input clock by any integer value between 2 and 16, inclusive.
• When using a 44MHz CLKIN, as is typical for 802.11 or
802.11b controllers with a PC Card Host Interface, common
divisors are 4 (11MHz) or 5 (8.8MHz)
FIGURE 10. TRANSMIT CONTROL SIGNAL SEQUENCING
PE1
PE2
TR_SW
TR_SW_BAR
PA_PE
tD1
tD5
tD3
tD4
TABLE 1. TRANSMIT CONTROL TIMING SPECIFICATIONS
PARAMETER
SYMBOL
DELAY
TOLERANCE UNITS
PE2toPA_PE
tD1
0.1
±0.1
µs
TPE2 to TR Switch
tD3
1.5
±0.1
µs
TR Switch to PE2
tD4
3
±0.1
µs
PA_PE to PE2
tD5
1
±0.1
µs
TABLE 2. POWER ENABLE STATES
PE1
PE2
PLL_PE
Power Down State
001
Receive State
1
1
1
Transmit State
101
PLLActiveState
0
1
1
PLL Disable State
X
X
0
PLL_PE is controlled via the serial interface, and can be used to
disable the internal synthesizer, the actual synthesizer control is an
AND function of PLL_PE, and a result of the OR function of PE1
and PE2. PE1 and PE2 will directly control the power enable
functionality of the LO buffer(s)/phase shifter.
ISL3873A


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