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ISL3873A Datasheet(PDF) 12 Page - Intersil Corporation

Part No. ISL3873A
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873A Datasheet(HTML) 12 Page - Intersil Corporation

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12
External Memory Interface
The ISL3873A provides separate external chip selects for
code space and data storage space. Code space is
accessible as data space through an overlay mechanism,
except for an internal ROM. Refer to Figures 6, 7 and 8 for
ISL3873A memory configuration detail examples.
The maximum possible memory space size is 4Mbytes. If
USB is the host interface, this is reduced to 1Mbyte.
Most of the data store space is reserved for storage of
received and transmitted data, with some areas reserved for
use by firmware. However, a portion of the data store may be
allocated as code store. This permits higher speed
instruction execution, by using fast RAMs, than is possible
from Flash memories. The maximum size of this overlay is
the full code space address range, 128Kbytes, and is
allocated in independent sections of 16KBytes each, on
16Kbyte boundaries, ranging from the highest address of the
actual physical memory space and extending down.
Mapping code execution to RAM requires the RAM to have
code written into it. Typically, this is done by placing code in a
non-volatile memory such as a Flash in the code space. At
initialization, the code in the non-volatile memory transfers itself
to RAM, maps the appropriate blocks of the code space to the
RAM, and then branches to begin execution from RAM. This
allows low cost, slow Flash devices to hold an entire code
image, which can be executed much faster from RAM. If code
is not placed in an external non-volatile memory as described
here, it must be transferred to the RAM via the Host Interface.
Slow memories are not dynamically sensed. Following reset,
the instruction clock operates with a slower cycle while the
Flash is copied to RAM. Once code has been copied from
Flash to RAM, execution transfers to RAM and the clock is
raised to the normal operating frequency.
As mentioned above, it is feasible to operate without a code
image in a non-volatile memory. In such a system, the
firmware must be downloaded to RAM through the host
interface before operation can commence.
The external SRAM memory must be organized in a 16-bit
width to provide adequate performance to implement the
802.11 protocol at 11Mb/s rates. Systems designed for lower
performance applications may be able to use 8-bit wide
memory.
The minimum external memory is 128Kbytes of SRAM,
organized 8 or 16 bits wide. Typical applications, including
802.11 station designs, use 256Kbytes organized 128K x 16.
An access point application could make use of the full address
space of the device with 4Mbytes organized a 2M x 16.
The ISL3873A supports 8 or 16-bit code space, and 8 or 16-
bit data space. Code space is typically populated with the
least expensive Flash memory available, usually an 8-bit
device. Data space is usually populated with high-speed
RAMs configured as a 16-bit space. This mixing of 8/16 bit
spaces is fully supported, and may be done in any
combination desired for code and data space.
The ISL3873A supports direct control of single chip 16-bit
wide SRAMs with high/low byte enables, as well as direct
control of a 16-bit space constructed from 8-bit wide SRAMs.
The type of memory configuration is specified via the
appropriate MD pin, sensed when the ISL3873A is reset.
ISL3873A pin MUBE-/MA0/MWEH- functions as Address 0
for 8-bit access, (such as Flash) as MWEH (High Byte Write
Enable) when two x8 memories are configured as a single
x16 space, and as the upper Byte Enable when a single x16
memory is used. No external logic is required to generate
the required signals for both types of memory configurations,
even when both exist together; all that is required is for the
ISL3873A code to configure the ISL3873A memory
controller to generate the proper signals for the particular
address space being accessed.
PULLUP
45DB011
PULLUP
CS# (TCLKIN)
SCLK (PJ0)
SD (PJ1)
MISO (PJ2)
ISL3873A
LARGE SERIAL EEPROM
SMALL SERIAL EEPROM
ISL3873A
PULLUP
CS# (TCLKIN)
SCLK (PJ0)
NOTE: Must operate at 400kHz AT 3.3VDC
24C08 (NOTE)
A2
A1
AO
SDA
SCL
WP
FIGURE 8. SERIAL EEPROM INTERFACE
SI
SCK
SO
RESET#
WP#
CS
ISL3873A


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