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ISL3873A Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL3873A Datasheet(HTML) 4 Page - Intersil Corporation |
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4 MAC Radio Interface and General Purpose Port Pins PIN NAME PIN I/O TYPE DESCRIPTION OF FUNCTION (IF OTHER THAN I/O PORT) PJ4 CMOS BiDir, 2mA PE1 PJ5 CMOSBiDir,2mA,50K Pull Up LE_IF PJ6 CMOS BiDir, 2mA LED1 PJ7 CMOS BiDir, 2mA, 50K Pull Up RADIO_PE PK0 CMOSBiDir,2mA,ST, 50K Pull Down LE_RF PK1 CMOS BiDir, 2mA, 50K Pull Down SYNTHCLK PK2 CMOS BiDir, 2mA, 50K Pull Down SYNTHDATA PK3 CMOS BiDir, 2mA PA_PE PK4 CMOS BiDir, 2mA PE2 PK7 CMOS BiDir, 2mA CAL_EN PL3 CMOS BiDir, 2mA TR_SW_BAR PL7 CMOSBiDir,2mA,Pull Down TR_SW SERIAL EEPROM PORT PINS PIN NAME PIN I/O TYPE DESCRIPTION PJ0 CMOS BiDir SCLK, Serial Clock PJ1 CMOS BiDir, 50K Pull Down SD, Serial Data Out PJ2 CMOS BiDir, 50K Pull Down MISO, Serial Data IN TCLKIN (CS_) CMOS BiDir CS_, Chip Select Clocks Port Pins PIN NAME PIN I/O TYPE DESCRIPTION CLKIN CMOS Input, 50K Pull Down External Clock Input to MCLK prescaler (at >= 2X Desired MCLK Frequency, Typically 44-48MHz) XTALIN Analog Input 32.768kHz Crystal Input XTALOUT CMOS Output, 2mA 32.768kHz Crystal Output CLKOUT CMOS, TS Output, 2mA Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0) BBP_CLK Input Baseband Processor Clock. The nominal frequency for this clock is 44MHz. This is used internally to generate divide by 2 and 4 for the transceiver clock Baseband Processor Receiver Port Pins PIN NAME PIN I/O TYPE DESCRIPTION RX_IF_AGC O Analog drive to the IF AGC control RX_RF_AGC O Drive to the RF AGC stage attenuator. CMOS digital RX_IF_DET I Analog input to the receive power A/D converter for AGC control RXI, ± I Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11- RXQ, ± I Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14- Baseband Processor Transmitter Port Pins PIN NAME PIN I/O TYPE DESCRIPTION TX_AGC_IN I Input to the transmit power A/D converter for transmit AGC control TX_IF_AGC O Analog drive to the transmit IF power control TXI ± O TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24- TXQ ± O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential 29+/30- ISL3873A |
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