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ISL3873A Datasheet(PDF) 27 Page - Intersil Corporation

Part No. ISL3873A
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873A Datasheet(HTML) 27 Page - Intersil Corporation

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Data Demodulation in the CCK Modes
In this mode, the demodulator uses Complementary Code
Keying (CCK) modulation for the two highest data rates. It is
slaved to the low rate processor which it depends on for
acquisition of initial timing and phase tracking information.
The low rate section acquires the signal, locks up symbol
and carrier tracking loops, and determines the data rate to
be used for the MPDU data.
The demodulator for the CCK modes takes over when the
preamble and header have been acquired and processed.
On the last bit of the header, the phase of the signal is
captured and used as a phase reference for the high rate
differential demodulator.
The signal from the A/D converters is carrier frequency and
phase corrected by a DESPIN stage. This removes the
frequency offset and aligns the I and Q Channels properly for
the correlators. The sample rate is decimated to 11MSPS for
the correlators after the DESPIN since the data is now
synchronous in time. There are 64 I and 64 Q channel
correlator outputs.
The demodulator knows the symbol timing, so the
correlation is batch processed over each symbol. The
correlation outputs from the correlator are compared to
each other in a biggest picker and the chosen one
determines 7 bits of the symbol. The phase of the chosen
one determines one more bits for a total of 8 bits per
symbol. Seven bits come from which of the 128 correlators
had the largest output and the last is determined from the
differential demod of the phase. In the 5.5Mbps mode, only
8 of the correlator outputs are monitored. This demodulates
3 bits for which of 8 correlators had the largest output and
one more for the phase demodulation of that output for a
total of 4 bits per symbol.
Equalizer Description
The ISL3873A employs a Decision Feedback Equalizer
(DFE) to improve performance in the presence of significant
multipath distortion. The DFE combats Inter Chip
Interference (ICI) and Inter Symbol Interference (ISI). The
equalizer is trained on the sample data collected during the
first part of the acquisition after the AGC has settled and the
antenna selected. The same data is used for CMF
calculations and equalizer training. Once the equalizer has
been set up, it is used to process the incoming symbols in a
decision feedback manner. After the Fast Walsh transform is
performed, the detected symbols are corrected for ICI before
the bigger picker where the symbol decision process is
performed. Once a symbol has been demodulated, the
calculated residual energy from that symbol is subtracted
from the incoming data for the next symbol. That corrects for
the ISI component. The DFE is not adapted during the
packet as the channel impulse response is not expected to
vary significantly during that brief time. Register CR10 bits 4
and 5 can disable these equalizers separately.
Tracking
Carrier tracking is performed on the de-rotated signal
samples from the complex multiplier in a four phase Costas
loop. This forms the error term that is integrated in the lead/lag
filter for the NCO, closing the loop. Tracking is only measured
when there is a chip transition. Note that this tracking is
dependent on a positive SNR in the chip rate bandwidth.
The symbol clock is tracked by a sample interpolator that
can adjust the sample timing forwards and backwards by 72
increments of 1/8th chip. This approach means that the
ISL3873A can only track an offset in timing for a finite
interval before the limits of the interpolator are reached.
Thus, continuous demodulation is not possible.
Locked Oscillator Tracking
Symbol tracking canbeslavedto the carrier offset tracking
for improved performance as long as at both the transmitting
and the receiving radios, the bit clocks and carrier frequency
clocks are locked to common crystal oscillators. A bit carried
in the SERVICE field (bit 2) indicates whether or not the
transmitter has locked clocks. When the same bit is set at
the receiver (CR6 bit 2), the receiver knows it can track the
bit clock by counting down the carrier tracking offset. This is
much more accurate than tracking the bit clock directly.
CR33 bit 6 can enable or disable this capability.
T0 + 1 SYMBOL CORRELATOR
CORRELATION
T0 + 2 SYMBOLS
T0
SAMPLES
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 18. CORRELATION PROCESS
PEAK
AT 2X CHIP
RATE
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL
OUTPUT REPEATS
ISL3873A


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