7

SYSTEM INTERFACE - PC CARD IO READ 16

Data Delay After HIORD-

--

100

ns

Data Hold Following HIORD-

0-

-

ns

HIORD- Width Time

165

-

-

ns

Address Setup Before HIORD-

70

-

-

ns

Address Hold Following HIORD-

20

-

-

ns

HCE(1, 2)- Setup Before HIORD-

5-

-

ns

HCE(1, 2)- Hold After HIORD-

20

-

-

ns

HREG- Setup Before HIORD-

5-

-

ns

HREG- Hold Following HIORD-

0-

-

ns

HINPACK- Delay Falling from HIORD-

0

-

45

ns

HINPACK- Delay Rising from HIORD-

30

-

45

ns

Data Delay from HWAIT- Rising

--

0

ns

HWAIT- Width Time

-

-

12,000

ns

SYSTEM INTERFACE - PC CARD IO WRITE 16

Data Setup Before HIORD-

30

-

92

ns

Data Hold Following HIORD-

20

-

-

ns

HIOWR- Width Time

165

-

-

ns

Address Setup Before HIORD-

70

-

-

ns

Address Hold Following HIORD-

20

-

-

ns

HCE(1, 2)- Setup Before HIORD-

5-

-

ns

HCE(1, 2)- Hold Following HIORD-

20

-

-

ns

HREG- Setup Before HIORD-

5-

-

ns

HREG- Hold Following HIORD-

0-

-

ns

HWAIT- Delay Falling from HIORD-

-

-

35

ns

HWAIT- Width Time

-

-

12,000

ns

HIOWR- High from HWAIT- High

0-

-

ns

RADIO TX DATA - TX PATH

TXC Period

--

ns

TXC Width Hi

31

-

-

ns

TXC Width Lo

31

-

-

ns

RADIO RX DATA - RX PATH

RX_RDY Setup Time to RXC Positive Edge (See Note 5)

10

-

-

ns

RX_RDY Hold Time from RXC Positive Edge (See Note 6)

45

-

-

ns

RX_PE2 Delay from RX_RDY deAssert (See Note 10)

-ns

RX_PE2 Low Pulse Width (See Note 9)

-ns

RXD Setup Time to RXC Positive Edge (See Note 7)

10

-

-

ns

RXD Hold Time from RXC Positive Edge (See Note 7)

0-

-

ns

RXC Period (See Note 12)

-ns

RXC Width Hi

31

-

-

ns

RXC Width Lo

31

-

-

ns

NOTES:

5. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is

sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.

6. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held

active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY

(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP

header length field are received. Therefore, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal

be cleared when the last RXD bit is received the hold time w/r RXC must be honored.

7. RXC positive edge clocks a flop which stores the RXD for internal usage.

8. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low.

9. RX_PE inactive width at BBP is 3 BBP CLK's. Since BBP CLK and MAC CLK can be async minimum should be 4 MAC CLKs.

10. When RX_RDY drops before expected number of RXD bits is received, then TX/RX FSM in mpctl.v signals timers which clear rx_pe2_int.

AC Electrical Specifications

(Continued)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

HFA3842B