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HFA3842AIN-TK Datasheet(PDF) 19 Page - Intersil Corporation |
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HFA3842AIN-TK Datasheet(HTML) 19 Page - Intersil Corporation |
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19 / 27 page  19 SYNTHESIZER For the PRISM II, the synthesizer is programmed by firmware using different pins than the MMI. The HFA3842A will exchange data with the baseband during transmit and receive operations over the MMI interface. If the MMI interface was connected to the front end chips, the transitions on SCLK and SD could couple noise into them. The synthesizer serial bus consists of SYNTHDATA, SYNTHCLK, LE_IF and LE_RF. SYNTHDATA is on pin PK2, SYNTHCLK is on PK1, LE_IF is the enable for the HFA3783 Quad IF chip, and LE_RF is the enable for the HFA3683 synthesizer. Data is provided on SYNTHDATA and clock on SYNTHCLK. The data is updated the falling edge of SYNTHCLK and expected to be latched into the synthesizer on the rising edge. The enable signal LE_RF is asserted while data is clocked out. PHY Data Interface (MDI) The HFA3842A has a dedicated serial port to provide the data interface to the baseband processor. This is referred to as the Modem Data Interface (MDI). The MDI operates on the data being transferred to and from the baseband on a word by word basis. There are no FIFOs needed, since the firmware is able to control the protocol in real time. The MDI performs the following functions: • Serial to parallel conversion of received data from the baseband, with synchronization between the incoming RX clock to the internal HFA3842A clock. • Generating CRCs (HEC and FCS) from the received data stream to verify correct reception. • Decrypt the received data when WEP is enabled. • Parallel to serial conversion of transmit data, with the serial timing synchronized with the TX clock. • Insertion of the CRCs (HEC and FCS) at the appropriate point during transmission. • Encrypt the transmitted data when WEP is enabled. The receive data path uses RX_RDY, RXC, RXD. The transmit data path uses TX_RDY, TXC, TXD and the CCA input to determine (under the IEEE802.11 protocol) whether to transmit. tSCP tSCW tSCW tSCS tSCH tSCD tSCED tSCED SCLK SDI, R/W, SD, CS SD (AS OUTPUT) R/W SD FIGURE 19. BBP CONTROL PORT SIGNAL TIMING TABLE 7. BBP CONTROL PORT AC ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL MIN MAX UNITS SCLK Clock Period tSCP 90 - ns SCLK Width Hi or Low tSCW 20 - ns SetuptoSCLK + Edge (SD, SDI, R/W, CS) tSCS 30 - ns Hold Time from SCLK + Edge (SD, SDI, R/W, CS) tSCH 0- ns SD Out Delay from SCLK + Edge tSCD -30 ns SD Out Enable/Disable from R/W tSCED -15 ns FIGURE 20. SYNTHESIZER DATA FORMAT LE_RF SYNTHCLK SYNTHDATA D23 D22 D21 D20 D1 D0 HFA3842A |
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