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HFA3842B Datasheet(PDF) 22 Page - Intersil Corporation

Part No. HFA3842B
Description  PCMCIA/USB Wireless LAN Medium Access Controller
Download  26 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842B Datasheet(HTML) 22 Page - Intersil Corporation

 
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TABLE 9. BBP TRANSMIT PORT AC ELECTRICAL
SPECIFICATIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
TX_PE to IOUT/QOUT
(1st Valid Chip)
tD1
2.18
2.3
µs(Note 17)
TX_PE Inactive Width
tTLP
2.22
-
µs(Note 18)
TXC Width Hi or Low
tTCD
40
-
ns
TXRDY Active to 1st
TX_CLK Hi
tRC
260
-
ns
Setup TXD to TXC Hi
tTDS
30
-
ns
Hold TXD to TXC Hi
tTDH
0-
ns
TXC to TX_PE
Inactive (1MBps)
tPEH
0
965
ns (Note 20)
TXC to TX_PE
Inactive (2MBps)
tPEH
0
420
ns (Note 20)
TXC to TX_PE
Inactive (5.5MBps)
tPEH
0
160
ns (Note 20)
TXC to TX_PE
Inactive (11MBps)
tPEH
065
ns (Note 20)
TXRDY Inactive To
Last Chip of MPDU
Out
tRI
-20
20
ns
TXD Modulation
Extension
tME
2-
µs(Note 19)
NOTES:
17. IOUT/QOUT are modulated before first valid chip of preamble is
output to provide ramp up time for RF/IF circuits.
18. TX_PE must be inactive before goingactivetogenerateanew
packet.
19. IOUT/QOUT are modulated after last chip of valid data to provide
ramp down time for RF/IF circuits.
20. Delay from TXC to inactive edge of TXPE to prevent next TXC.
Because TXPE asynchronously stops TXC, TXPE going inactive
within 40ns of TXC will cause TXC minimum hi time to be less
than 40ns.
TABLE 9. BBP TRANSMIT PORT AC ELECTRICAL
SPECIFICATIONS (Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC.
FIGURE 23. BBP TRANSMIT PORT TIMING
TXC
TX_PE
TXD
TXRDY
FIRST DATA BIT SAMPLED
LSB
MSB
DATA PACKET
LAST DATA BIT SAMPLED
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3861
FIGURE 24. BBP TRANSMIT PORT SIGNAL TIMING
tPEH
tTLP
tME
tRI
tTCD
tTCD
tRC
tTDH
tTDS
tDI
TX_PE
IOUT, QOUT
TXRDY
TXC
TXD
HFA3842B


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