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HFA3842B Datasheet(PDF) 21 Page - Intersil Corporation

Part No. HFA3842B
Description  PCMCIA/USB Wireless LAN Medium Access Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842B Datasheet(HTML) 21 Page - Intersil Corporation

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21
BBP Packet Transmission
There are 4 signals associated with the BBP Transmit Port:
TX_PE (Transmit Enable), TXRDY (Transmit Ready), TXD
(Transmit Data), and TXCLK (Transmit Clock). These
connect to the HFA3842B on PL0, PL7, TXD, and TXC,
respectively.
State machines within the BBP control packet transmission
and reception. In the case of a transmission, the MAC
signals the BBP with the signal TX_PE. The BBP forms the
preamble and header and then signals the MAC to begin
transferring data with the signal TXRDY. This sequence is
illustratedinFigure22withdetailedsignal timingshownin
Figure 23 and specified delays contained in Table 9. Note
that if the MAC deactivates TX_PE too early it may cut off
modulation of the final symbol. For this reason, when
TX_PE is de-asserted the BBP will hold TXRDY active until
the last symbol containing data is modulated. This is
important for power sequencing and is discussed in more
detail in that section.
For more detailed information concerning BBP packet
transmission see the HFA3861 data sheet.
USB Port
The USB interface implemented in the HFA3842B complies
with the Universal Serial Bus Specification Revision 1.1.
dated September 23, 1998, which is available from the USB
Implementers’ Forum at http://www.usb.org/.
The USB host port interface uses Microsoft’s Remote NDIS
protocol to communicate with the network software on the
host computer. The USB supports 4 endpoints.
• One Communications Class control endpoint for interface
management;
• One Communications Class interrupt endpoint for
signalling interrupts to the host; and
• Two Bulk endpoints for transfer of encapsulated NDIS
functions to and from the host.
TABLE 8. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
RX_PE Inactive Width
tRLP
70
-
ns (Note 11)
RXC Period (11MBps Mode)
tRCP
77
-
ns
RXC Width Hi or Low (11MBps Mode)
tRCD
31
-
ns
RXC to RXD
tRDD
20
60
ns
MD_RDY to 1st RXC
tRD1
940
-
ns (Note 12)
RXD to 1st RXC
tRD!
940
-
ns
Setup RXD to RXC
tRDS
31
-
ns
RXC to RX_PE Inactive (1MBps)
tREH
0
925
ns (Note 13)
RXC to RX_PE Inactive (2MBps)
tREH
0
380
ns (Note 13)
RXC to RX_PE Inactive (5.5MBps)
tREH
0
140
ns (Note 13)
RXC to RX_PE Inactive (11MBps)
tREH
050
ns (Note 13)
RX_PE inactive to MD_RDY Inactive
tRD2
530
ns (Note 14)
Last Chip of SFD in to MD_RDY Active
tRD3
2.77
2.86
µs(Note 12)
RX Delay
2.77
2.86
µs(Note 15)
RX_PE to CCA Valid
tCCA
-10
µs(Note 16)
RX_PE to RSSI Valid
tCCA
-10
µs(Note 16)
NOTES:
11. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
12. MD_RDY programmed to go active after SFD detect (measured from IIN,QIN).
13. RX_PE active to inactive delay to prevent next RXC.
14. Assumes RX_PE inactive after last RXC.
15. MD_RDY programmedtogoactiveat MPDU start. Measuredfromfirst chip of first MPDU symbol at IIN,QIN to MD_RDY active.
16. CCA and RSSI are measured once during the first 10
µs interval following RX_PE going active. RX_PE must be pulsed to initiate a new
measurement. RSSI may be read via serial port or from Test Bus.
HFA3842B


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