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HFA3842B Datasheet(PDF) 20 Page - Intersil Corporation

Part No. HFA3842B
Description  PCMCIA/USB Wireless LAN Medium Access Controller
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HFA3842B Datasheet(HTML) 20 Page - Intersil Corporation

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In transmit mode, the HFA386X is used in the mode where it
generates the PLCP header internally and only the MPDU is
passed from HFA3842B. In receive, the HFA386X is used in
the mode where it passes the PLCP header and the MPDU
to the HFA3842B.
BBP Packet Reception
There are 4 signals associated with the BBP Receive Port:
RX_PE (Receive Enable), MDRDY (Receive Ready), RXD
(Receive Data), and RXCLK (Receive Clock). These
connect to the HFA3842B on pins PL1, PK5, RXD, and RXC,
respectively.
The receive demodulator in the BBP is activated via RX_PE.
When RX_PE goes active the demodulator scrutinizes I and
Q for packet activity. When a packet arrives at a valid signal
level the demodulator acquires and tracks the incoming
signal. It then sifts through the demodulator data for the Start
Frame Delimiter (SFD). Normally, MDRDY is programmed to
go active after SFD is detected. This signals the HFA3842B,
allowing it to pick off the needed header fields from the real-
time demodulated bitstream rather than having to read these
fields through the BBP Control Port.
Assuming all is well with the header, the BBP decodes the
signal field in the header and switches to the appropriate
data rate. If the signal field is not recognized, or the CRC16
is in error, then MDRDY will go inactive shortly after CRC16
and the demodulator will return to acquisition mode looking
for another packet. If all is well with the header, and after the
demodulator has switched to the appropriate data rate, then
the demodulator will continue to provide data to the
HFA3842B indefinitely.
Receive Port exchange details are depicted in Figure 21.
Detailed timing is related in Figure 22 and Table 8.
For more detailed information concerning BBP packet
reception see the HFA386x data sheets.
FIGURE 21. BBP RECEIVE PORT TIMING
LSB
MSB
DATA PACKET
RXC
RX_PE
MDRDY
RXD
HEADER
FIELDS
PROCESSING
PREAMBLE/HEADER
DATA
RX_PE
IIN,QIN
tRLP
MDRDY
RXC
RXD
CCA, RSSI
tCCA
tRD3
tRDI
tRCD
tRCP
tREH
tRD2
FIGURE 22. BBP RECEIVE PORT SIGNAL TIMING
NOTE: RXD, MDRDY is output two MCLK after RXC rising to provide hold time. RSSI output on TEST (5:0).
tRCD
tRDD
tRDS
HFA3842B


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