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HFA3842B Datasheet(PDF) 18 Page - Intersil Corporation |
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HFA3842B Datasheet(HTML) 18 Page - Intersil Corporation |
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18 / 26 page  18 PHY BASEBAND PROCESSOR The PHY baseband processor is programmed by HFA3842B firmware. The PRISM II baseband processor mode works as follows: The Control Port consists of 3 signals: SD (serial data), SCLK (serial clock), and CS_BAR (active-low chip select). Control Port signaling for read and write operations is illustrated in Figures 17 and 18 respectively. Detailed timing relationships appear in Figure 19 and timing specifications are contained in Table 7. The BBP always uses the rising edge when clocking data on the Control Port. This means that when the BBP is receiving data it uses the rising edge of clock to sample; when driving data, transitions occur on the rising edge. Address bits 6 through 1 are significant for selecting configuration registers. Address bits 7 and 0 are unused. See the BBP Programming section for register addresses and suggested values. For read operations, the rising edge of R/W must occur after the 7th but prior to the 8th rising edge of SCLK. This ensures that the first data bit is clocked out of the BBP prior to the edge used to clock it into the MAC. For more detailed information on the Control Port and BBP register programming see the HFA386x data sheets. FIGURE 16. BLOCK DIAGRAM OF A BUFFER ACCESS PATH BUFFER DESCRIPTOR ACCESS (FIRMWARE) ALLOCATE/ DEALLOCATE REQUEST BLOCK OFFSET VIRTUAL FRAME BUFFER DATA PORT PRE-READ/ POST-WRITE OFFSET CENTER HOST BUS STATUS HEADER DATA BUFFER MEMORY A FID D 7 6 54 3 2 1 0 7 6 5 4 32 1 0 7 6 5 4 32 1 0 76 5 4 3 2 76 1 0 SCLK FIRST DATABIT OUT MSB ADDRESS IN DATA OUT MSB LSB FIRST ADDRESS BIT SD R/W CS FIGURE 17. PRISM II BASEBAND PROCESSOR CONTROL PORT READ TIMING 7 6 5 4 32 10 7 6 54 3 2 10 7 6543 2 10 7 6 5 4 3 2 1 0 SCLK MSB ADDRESS IN MSB DATA IN LSB SD R/W CS FIGURE 18. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING HFA3842B |
Similar Part No. - HFA3842B |
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Similar Description - HFA3842B |
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