10
201-0000-033 Rev 1.0, 6/2/99
CHRONTEL
CH5101A
I2C Port Operation
The CH5101 contains a standard I2C control port, through which the control registers can be written and read. This
port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to
the SDB and SCB buses as shown in Figure 5.
The Serial Clock line (SC) is input only and is driven by the output buffer of the master device. The CH5101 acts as
a slave and generation of clock signals on the bus is always the responsibility of the master device. When the bus is
free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-
collector to perform the wired-AND function. Data on the bus can be transferred up to 400kbit/s according to I2C
specifications. However, in direct connections to the bus master device, the CH5101 can operate at transfer rates up
to 5 MHz.
Figure 5: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected
to them are shown in Figure 5. A pullup resistor (RP) must be connected to a 5V ± 10% supply. The CH5101 is a
device with input levels related to VDD.
Maximum and minimum values of pullup resistor (RP)
The value of RP depends on the following parameters:
• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = Iinput)
The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 3mA at
VOLmax = 0.4 V for the output stages:
RP >= (VDD – 0.4) / 3 (RP in kΩ)
The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum
value of RP due to the specified rise time. The equation for RP is shown below:
RP >= 10
3/C (where: R
P is in kΩ and C, the total capacitance, is in pF)
The maximum HIGH level input current of each input/output connection has a specified maximum value of 10
µA.
Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP.
SCLK
IN2
DATA
IN2
DATAN2
OUT
SCB (Serial Clock Bus)
SDB (Serial Data Bus)
+VDD
RP
SLAVE
SCLK
IN1
DATA
IN1
DATAN2
OUT
SLAVE
SCLK
OUT
FROM
MASTER
DATA IN
MASTER
DATAN2
OUT
MASTER
BUS MASTER
SC
SD
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