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MC44605 Datasheet(PDF) 10 Page - ON Semiconductor |
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MC44605 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 20 page MC44605 http://onsemi.com 10 is 9.4 V (maximum value of Vdisable 1) and so the minimum hysteresis is 4.2 V. [(Vstup–th)min = 13.6 V]. The large hysteresis and the low start–up current of the MC44605 make it ideally suited for off–line converter applications where efficient bootstrap start–up techniques are required. Soft–Start Control Section The Vcs value is clamped down to the pin 11 voltage. So, if a capacitor is connected to this pin, its voltage increases slowly at the start–up (the capacitor is charged by an internal current source 0.4 Iref). So, Vcs is limited during the start–up and then a soft–start is performed. This pin can be used to inhibit the circuit by applying a voltage that is lower than VSSinhi (refer to page 4). Particularly, the MC44605 can be shutdown by connecting the soft–start pin to ground. As soon as Vdis1 is detected (that is Vcc lower than Vdisable1), a signal UVLO1 is generated until the Vcc falls down to Vdis2 (refer to the undervoltage lockout section §). During the delay between the disable1 and the disable2, using a transistor controlled by UVLO1, the pin 11 voltage is made equal to zero in order to make the soft–start arrangement ready to work for the next re–start. Figure 4. Soft–Start MC44605 Vref UVLO1 Soft Start Capacitor Vcs 0.4 Iref VSSlnhi Output Inhibition Pin 11 2.4 V DZ Oscillator Section (Figures 5 & 5b) The oscillator and synchronization behavior is represented in Figure 5b. The MC44605 oscillator achieves four functions: — it fixes the free mode frequency — it takes into account the synchronization signal — it does not allow a new power switch conduction if the flyback is not in a dead–time state when the circuit works in demagnetization mode (pin 8 connected) — it builds the Sf pulse required by the MPL block During the operating mode, the oscillator sawtooth can vary between a valley value (1.6 V typically) and a peak one (3.6 V typically) and presents three distinct phases: — the CT charge — the CT discharge — the phase during which the oscillator voltage is maintained equal to its valley value. This happens at the end of a discharge cycle when the synchronization or demagnetization condition does not allow a new CT charge phase. During this sequence, IREGUL compensates the charge current Icharge. The oscillator has two working modes: — a free one when there is no synchronization — a synchronized one. In the free working, the oscillator grows up from its valley value to its peak one for the charge phase and when once the peak value is reached, a discharge sequence makes the CT voltage decrease down to its valley value. When the decrease phase is finished, a new charge cycle occurs if the demagnetization condition is achieved (VDT high). Otherwise there is a REGUL phase until VDT gets high. In the synchronized mode, the charge cycle is only allowed when the synchronization signal gets high while a dead time has been detected (VDT high). This charge phase is stopped when the synchronization signal has got low and when the oscillator voltage is higher than Vint, the intermediary voltage level used to generate the calibrated pulse Sf by comparing the CT voltage to this threshold. So, when these two conditions are performed, a discharge sequence is set until the oscillator voltage is equal to its valley value. Then, the CT voltage is maintained constant thanks to the “REGUL” arrangement until the next synchronization pulse. In both cases, during the charge phase, a signal VS is generated. When Sf becomes high. VS gets high and remains in this state until the PWN latch is set of Sf is low. Then, VS keeps low until the next Sf high level. This oscillator behavior is obtained using the process described in Figure 5b. |
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