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2

Unit Loading/Fan Out

Functional Description

The 74F162A count modulo-10 in the BCD (8421)

sequence. From state 9 (HLLH) they increment to state 0

(LLLL). The clock inputs of all flip-flops are driven in paral-

lel through a clock buffer. Thus all changes of the Q outputs

occur as a result of, and synchronous with, the LOW-to-

HIGH transition of the CP input signal. The circuits have

four fundamental modes of operation, in order of prece-

dence: synchronous reset, parallel load, count-up and hold.

Four control inputs— Synchronous Reset (SR), Parallel

Enable (PE), Count Enable Parallel (CEP) and Count

Enable Trickle (CET)—determine the mode of operation,

as shown in the Mode Select Table. A LOW signal on SR

overrides counting and parallel loading and allows all out-

puts to go LOW on the next rising edge of CP. A LOW sig-

nal on PE overrides counting and allows information on the

the next rising edge of CP. With PE and SR HIGH, CEP

and CET permit counting when both are HIGH. Conversely,

a LOW signal on either CEP or CET inhibits counting.

The F162A uses D-type edge-triggered flip-flops and

changing the SR, PE, CEP and CET inputs when the CP is

in either state does not cause errors, provided that the rec-

ommended setup and hold times, with respect to the rising

edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is

HIGH and counter is in state 9. To implement synchronous

multistage counters, the TC outputs can be used with the

CEP and CET inputs in two different ways. Please refer to

the F568 datasheet. The TC output is subject to decoding

spikes due to internal race conditions and is therefore not

recommended for use as a clock or asynchronous reset for

flip-flops, counters or registers. In the F162A decade

counters, the TC output is fully decoded and can only be

HIGH in state 9. If a decade counter is preset to an illegal

state, or assumes an illegal state when power is applied, it

will return to the normal sequence within two counts, as

shown in the State Diagram.

Logic Equations:

Count Enable

= CEP × CET × PE

TC

= Q

Mode Select Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

State Diagram

Pin Names

Description

U.L.

CEP

Count Enable Parallel Input

1.0/1.0

20

µA/−0.6 mA

CET

Count Enable Trickle Input

1.0/2.0

20

µA/−1.2 mA

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

SR

Synchronous Reset Input (Active LOW)

1.0/2.0

20

µA/−1.2 mA

Parallel Data Inputs

1.0/1.0

20

µA/−0.6 mA

PE

Parallel Enable Input (Active LOW)

1.0/2.0

20

µA/−1.2 mA

Flip-Flop Outputs

50/33.3

−1 mA/20 mA

TC

Terminal Count Output

50/33.3

−1 mA/20 mA

SR

PE

CET CEP

Action on the Rising

Clock Edge (

)

L

X

X

X

Reset (Clear)

H

L

X

X

H

H

H

H

Count (Increment)

H

H

L

X

No Change (Hold)

H

H

X

L

No Change (Hold)