PE3239EK datasheet(5/12 Pages) PEREGRINE

Part #	PE3239EK

Description	2.2 GHz Integer-N PLL for Low Phase Noise Applications

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

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Product Specification

PE3239

Page 5 of 12

Document No. 70-0047-02

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Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Note 1:

fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk

specification.

Note 2:

CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum

phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.

Note 3:

Parameter is guaranteed through characterization only and is not tested.

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 6, 7, 8)

fClk

Serial data clock frequency

(Note 1)

10

MHz

tClkH

Serial clock HIGH time

30

ns

tClkL

Serial clock LOW time

30

ns

tDSU

Sdata set-up time to Sclk rising edge

10

ns

tDHLD

Sdata hold time after Sclk rising edge

10

ns

tPW

S_WR pulse width

30

ns

tCWR

Sclk rising edge to S_WR rising edge

30

ns

tCE

Sclk falling edge to E_WR transition

30

ns

tWRC

S_WR falling edge to Sclk rising edge

30

ns

tEC

E_WR transition to Sclk rising edge

30

ns

Main Divider (Including Prescaler)

Fin

Operating frequency

200

2200

MHz

PFin

Input level range

External AC coupling

-5

5

dBm

Main Divider (Prescaler Bypassed)

Fin

Operating frequency

20

220

MHz

PFin

Input level range

External AC coupling

-5

5

dBm

Reference Divider

fr

Operating frequency

(Note 3)

100

MHz

Pfr

Reference input power (Note 2)

Single ended input

-2

dBm

Phase Detector

fc

Comparison frequency

(Note 3)

20

MHz

SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)

100 Hz Offset

-75

dBc/Hz

1 kHz Offset

-85

dBc/Hz

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