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CLRC63201T Datasheet(PDF) 9 Page - NXP Semiconductors

Part # CLRC63201T
Description  Standard multi-protocol reader solution
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC63201T Datasheet(HTML) 9 Page - NXP Semiconductors

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CLRC632
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 27 February 2014
073937
9 of 127
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.1.3.2
Common read and write strobe
Refer to Section 13.4.2 on page 103 for timing specification.
9.1.3.3
Common read and write strobe: EPP with handshake
Refer to Section 13.4.3 on page 104 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The CLRC632 does not support Read Address Cycle.
9.1.4 Serial Peripheral Interface
The CLRC632 provides compatibility with the 5-wire Serial Peripheral Interface (SPI)
standard and acts as a slave during the SPI communication. The SPI clock signal SCK
must be generated by the master. Data communication from the master to the slave uses
the MOSI line. The MISO line sends data from the CLRC632 to the master.
Fig 4.
Connection to microprocessor: common read and write strobes
001aak608
address bus (A3 to An)
NCS
A0 to A2
address bus (A0 to A2)
D0 to D7
ALE
data bus (D0 to D7)
HIGH
NRD
Data strobe (NDS)
NWR
Read/Write (R/NW)
DEVICE
ADDRESS
DECODER
non-multiplexed address
NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
Address strobe (AS)
NRD
Data strobe (NDS)
NWR
Read/Write (R/NW)
A2
LOW
A1
HIGH
A0
LOW
DEVICE
ADDRESS
DECODER
Fig 5.
Connection to microprocessor: EPP common read/write strobes and handshake
001aak609
LOW
NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
Address strobe (nAStrb)
NRD
Data strobe (nDStrb)
NWR
Read/Write (nWrite)
A2
HIGH
A1
HIGH
A0
nWait
DEVICE


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