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CLRC63201T Datasheet(PDF) 7 Page - NXP Semiconductors |
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CLRC63201T Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 127 page CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 7 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The CLRC632 supports direct interfacing to various 8-bit microprocessors. Alternatively, the CLRC632 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the CLRC632. 9.1.2 Automatic microprocessor interface detection After a Power-On or Hard reset, the CLRC632 resets parallel microprocessor interface mode and detects the microprocessor interface type. The CLRC632 identifies the microprocessor interface using the logic levels on the control pins. This is performed using a combination of fixed pin connections and the dedicated Initialization routine (see Section 9.7.4 on page 30). Table 4. Supported microprocessor and EPP interface signals Bus control signals Bus Separated address and data bus Multiplexed address and data bus Separated read and write strobes control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe with handshake (EPP) control - nWrite, nDStrb, nAStrb, nWait address - AD0, AD1, AD2, AD3, AD4, AD5 data - AD0 to AD7 |
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