3.3V 4K/8K x 18
Synchronous Dual-Port Static RAM
CY7C09349AV
CY7C09359AV
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 13, 2000
1
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 4K x 18 organization (CY7C09349AV)
— 8K x 18 organization (CY7C09359AV)
• Three Modes
— Flow-Through
—Pipelined
—Burst
• Pipelined output mode on both ports allows fast 83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns (max.)
• 3.3V Low operating power
— Active = 135 mA (typical)
— Standby = 10
µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
Notes:
1.
A0–A11 for 4K; A0–A12 for 8K devices.
v
Logic Block Diagram
R/WL
1
0
0/1
CE0L
CE1L
LBL
OEL
UBL
1b
0/1
0b 1a 0a
ba
FT/PipeL
I/O9L–I/O17L
I/O0L–I/O8L
I/O
Control
Counter/
Address
Register
Decode
A0L–A11/12L
CLKL
ADSL
CNTENL
CNTRSTL
True Dual-Ported
RAM Array
R/WR
1
0
0/1
CE0R
CE1R
LBR
OER
UBR
1b
0/1
0b
1a
0a
b
a
FT/PipeR
I/O
Control
Counter/
Address
Register
Decode
12/13
9
9
I/O9R–I/O17R
I/O0R–I/O8R
A0R–A11/12R
CLKR
ADSR
CNTENR
CNTRSTR
12/13
9
9
[1]
[1]
For the most recent information, visit the Cypress web site at www.cypress.com
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