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ADC081500EVAL Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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ADC081500EVAL Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 28 page Pin Descriptions and Equivalent Circuits (Continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 104 105 106 107 111 112 113 114 115 116 117 118 122 123 124 125 Dd7− Dd7+ Dd6− Dd6+ Dd5− Dd5+ Dd4− Dd4+ Dd3− Dd3+ Dd2− Dd2+ Dd1− Dd1+ Dd0 Dd0 The LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the D outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100 Ω differential resistor. 79 80 OR+ OR- Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±325 mV or ±435 mV as defined by the FSR pin). 82 81 DCLK+ DCLK- Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 V A Analog power supply pins. Bypass these pins to ground. 40, 51 ,62, 73, 88, 99, 110, 121 V DR Output Driver power supply pins. Bypass these pins to DR GND. 1, 6, 9, 12, 21, 24, 27, 41 GND Ground return for V A. 42, 53, 64, 74, 87, 97, 108, 119 DR GND Ground return for V DR. www.national.com 5 |
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