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X96011V14IZ Datasheet(PDF) 5 Page - Intersil Corporation |
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X96011V14IZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 23 page 5 FN8215.1 October 25, 2005 D/A CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions) Notes: 1. LSB is defined as divided by the resistance between R1 or R2 to Vss. 2. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC. DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust- ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 3. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit Test Conditions / Notes IFS Iout full scale current 1.56 1.58 1.6 mA DAC input Byte = FFh, Source or sink mode, V(Iout) is Vcc–1.2V in source mode and 1.2V in sink mode. See notes 1 and 2. OffsetDAC Iout D/A converter offset error 1 1 LSB FSErrorDAC Iout D/A converter full scale error -2 2 LSB DNLDAC Iout D/A converter Differential Nonlinearity -0.5 0.5 LSB INLDAC Iout D/A converter Integral Nonlinearity with respect to a straight line through 0 and the full scale value -1 1 LSB VISink I1 Sink Voltage Compliance 1.2 Vcc V In this range the current at I1 vary < 1% VISource I1 Source Voltage Compliance 0 Vcc - 1.2 V In this range the current at I1 vary < 1% IOVER I1 overshoot on D/A Converter data byte transition 0 µA DAC input byte changing from 00h to FFh and vice versa, V(I1) is Vcc - 1.2V in source mode and 1.2V in sink mode. See note 3. IUNDER I1 undershoot on D/A Converter data byte transition 0 µA trDAC I1 rise time on D/A Converter data byte transition; 10% to 90% 530 µs TCOI1I2 Temperature coefficient of output current Iout ±200 ppm/°C See Figure 5. 2 3 V(VRef) 255 x [] X96011 |
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