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X80204V20I Datasheet(PDF) 7 Page - Intersil Corporation |
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X80204V20I Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 16 page  7 FN8154.0 Principles of Operation Power Sequencing Control (PSC) The Intersil X80200 supports a variety of sequencing applications. The sequencing can be voltage-based or time- based. Some examples are shown in Figure , Figure , and Figure in the Applications section. The X80200 allows for designs that can control the power sequencing of up to three voltage supplies. For systems with more than three supplies, the X80200 may be cascaded. Basic Functions VDDH is the primary voltage for the X80200. Once VDDH rises above the primary undervoltage lockout level (UVLOH) for time tPURST, the READY output goes HIGH indicating that the supply power is good. By connecting READY directly to GATEH_EN, the GATE_H output goes high immediately, turning on the power FET connected in series with VDDH. The system primary voltage may be delayed by using an external RC circuit between READY and GATEH_EN. VDDH must be stable before VDDM and VDDL supplies are monitored and power sequencing begins. The second supply voltage (I/O supply) is monitored by the VDDM pin. VDDM must be greater than the I/O supply undervoltage lockout level (UVLOM) prior to any activation of the GATE_M output. The VDDM voltage is used to turn on the charge pump that drives the GATE_M output. The third supply (core supply) is monitored by the VDDL pin. VDDL must be greater than the core supply undervoltage lockout level (UVLOL) prior to any activation of the GATE_L output. The VDDL voltage is used to turn on the charge pump that drives the GATE_M output. Power Sequencing Functions X80200 provides two options for power sequencing. In time based sequencing, the ENS (Enable Sequence) input signals that the core and I/O voltages are to turn on with a fixed time relationship. In voltage based sequencing, the SETV (Set Voltage) initiates turn-on of the core voltage. The I/O voltage remains off until the core voltage reaches a set threshold. In both cases the X80200 uses a core-voltage first and core voltage-last power up/down algorithm. TIME-BASED POWER SEQUENCING A rising edge (LOW to HIGH) transition of the ENS pin turns on the charge pump that drives the GATE_L output. A falling edge (HIGH to LOW) transition of the ENS signal turns off the charge pump that drives the GATE_M output. This technique provides a “forced” core-voltage-first power up and core-voltage-last power down algorithm. The ENS signal does not control the ramp up/down rates of the GATE_M or GATE_L outputs. In the absence of an externally provided ENS signal, the ENS pin can be connected in a number of different ways. • ENS can connect to the VDDH pin. In this case, the GATE_H and GATE_L outputs are enabled at the same time. GATE_H could be delayed by using an external RC timer between READY and GATEH_EN to provide a sequence where VDDL is the first supply voltage applied to the system. • ENS can connect to a delayed READY signal, so that the VDDL voltage follows the VDDH voltage by a fixed time. • ENS can connect to the system side of the VDDH FET, so the VDDL voltage will follow immediately after the primary supply is applied to the system. See "Functional Description" on page 7 for details on timing and ramp-up. VOLTAGE-BASED POWER SEQUENCING In this configuration, the drain of the “L” MOSFET is connected to the VFB input of the X80200, the ENS pin is tied to ground and a resistor divider provides a reference voltage to the REF pin. A LOW to HIGH transition of the SETV pin turns on the GATE_L output. This turns on the “L” MOSFET. Once the drain of this FET reaches the REF level, GATE_M turns on. Since the trigger for the GATE_M output is selected by a threshold level, the user has the ability to specify relative core and I/O voltage sequencing. System Monitoring and Remote Shutdown The X80200 Status Register contains fault detection bits that indicate the status of the GATE_H, GATE_M, and GATE_L pins. These bits are Stat_GATEH, Stat_GATEM, and Stat_GATEL. The status register can be read via 2-wire bus. This feature allows for system monitoring of the power sequencing of supplies. The system can turn off the FETs by writing to the Remote Shutdown Register through the 2-wire interface. There are three turn-off selections. See "Remote Shutdown Register (RSR) (Volatile)" on page 10 for more details. Functional Description Voltage Inputs. The X80200 has three voltage monitors for power sequencing: the VDDH (primary voltage), VDDM (I/O voltage), and VDDL (core voltage). These voltage monitors operate independently of each other. PRIMARY VOLTAGE VDDH This voltage is the primary voltage for the device and is required before X80200 can power sequence VDDM and VDDL. As VDDH powers up, it is compared to an internal UVLOH reference. This undervoltage lockout level is preset at the factory. For information on this setting, see Ordering Information. For custom programmed levels, contact Intersil. X80200, X80201, X80202, X80203, X80204 |
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