X80130 datasheet(8/18 Pages) INTERSIL

Part #	X80130

Description	Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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8 / 18 page

8

FN8152.0

January 20, 2005

Symbol Table

Pinout

Must be

steady

Will be

steady

May change

from LOW

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

WAVEFORM INPUTS

OUTPUTS

to HIGH

QFN package

(Top view)

V1GDO

V3GDO

DNC

V4MON

V3MON

V1MON

RESET

WP

V4GDO

SCL

1

2

3

4

5

67

18

19

20

8

17

(5mm x 5mm)

910

11

12

14

15

16

13

Pin Descriptions

NAME

DESCRIPTION

1V4GDO

V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4

and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin.

2V4MON

V4 Voltage Monitor Input. Third voltage monitor pin. If unused connect to VCC.

3V3GDO

V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than VREF3

and goes LOW when V3MON is greater than VREF3. There is user selectable delay circuitry on this pin.

4V3MON

V3 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC.

5

DNC

Do Not Connect.

6VP

EEPROM programming Voltage.

7VCC

Connect to VCC.

8

DNC

Do Not Connect.

9

A1

Address Select Input. It has an internal pull-down resistor. (>10M

Ω typical)

The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface.

10

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device.

It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires

a pull up resistor and the input buffer is always active (not gated).

11

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

12

V1MON

V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC.

13

V1GDO

V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1

and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin.

14

RESET

RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive

and the power sequencing is complete. This pin will be released after a programmable delay.

15

WP

Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the

device. It has an internal pull-down resistor. (>10M

Ω typical)

16

MR

Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5

µsecs. It has an

internal pull-down resistor. (>10M

Ω typical)

17

VSS

Ground Input.

18

NC

No Connect. No internal connections.

19

A0

Address Select Input. It has an internal pull-down resistor. (>10M

Ω typical)

The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface.

20

VCC

Supply Voltage.

X80130, X80131, X80132, X80133, X80134

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