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X40626S14I-2.7A Datasheet(PDF) 11 Page - Intersil Corporation |
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X40626S14I-2.7A Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 22 page 11 FN8119.0 March 28, 2005 Figure 11. Acknowledge Polling Sequence Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Ran- dom Reads, and Sequential Reads. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incre- mented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address in the address counter is 00H. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 12 for the address, acknowledge, and data transfer sequence. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Figure 12. Current Address Read Sequence ACK returned? Issue Slave Address Byte (Read or Write) Byte load completed by issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES Nonvolatile Cycle complete. Continue command sequence? Issue STOP NO Continue Normal Read or Write Command Sequence PROCEED YES S t a r t S t o p Slave Address Data SDA Bus Signals from the Slave Signals from the Master A C K S0 S1 1 10 10 0 X40626 |
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