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X40430V14I-B Datasheet(PDF) 3 Page - Intersil Corporation |
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X40430V14I-B Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 24 page 3 FN8251.0 July 29, 2005 PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40430, X40431, X40434, X40435 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40431, X40435) and RESET (X40430, X40434) pin allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button Manual Reset By connecting a push-button directly from MR to ground, the designer adds manual system reset capability. The MR pin is LOW while the push-button is closed and RESET/RESET pin remains HIGH/LOW until the push- button is released and for tPURST thereafter. 5MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re- main HIGH/LOW until the pin is released and for the tPURST thereafter. 6 RESET/ RESET RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when- ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when- ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. 7VSS Ground 8SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor (>10M Ω typical). 11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. Connect V3MON to VSS or VCC when not used. The V3MON comparator is supplied by the V3MON input. 12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin. 13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active. 14 VCC Supply Voltage PIN DESCRIPTION (Continued) Pin Name Function VCC MR System Reset Manual Reset X40430, X40434 RESET X40430, X40431, X40434, X40435 |
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