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X40626V14I-4.5A Datasheet(PDF) 3 Page - Intersil Corporation |
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X40626V14I-4.5A Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 22 page  3 FN8119.0 March 28, 2005 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X40626 activates a power- on Reset Circuit that pulls the RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP threshold value for tPURST (200ms nominal) the circuit releases RESET allowing the system to begin operation. LOW VOLTAGE MONITORING During operation, the X40626 monitors the VCC level and asserts RESET if supply voltage falls below a pre- set minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. WATCHDOG TIMER The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time-out period to prevent a RESET signal. The state of two nonvolatile control bits in the Status Register determine the watch- dog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. EEPROM INADVERTENT WRITE PROTECTION When RESET goes active as a result of a low voltage condition or Watchdog Timer Time-Out, any in- progress communications are terminated. While RESET is active, no new communications are allowed and no non-volatile write operation can start. Non-vol- atile writes in-progress when RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VCC/V2MON THRESHOLD RESET PROCEDURE The X40626 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applica- tions where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X40626 threshold may be adjusted. The procedure is described below, and uses the application of a nonvol- atile control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher or lower voltage value. It is necessary to reset the trip point before setting the new value. The VCC and V2MON must be tied together during this sequence. To set the new VTRIP voltage, start by setting the WEL bit in the control register, then apply the desired VTRIP threshold voltage to the VCC pin and the programming voltage, VP, to the WP pin and 2 byte address and 1 byte of “00” data. The stop bit following a valid write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Figure 1. Set VTRIP Level Sequence (VCC/V2MON = desired VTRIP values, WP = 12-15V when WEL bit set) 01 2 3 45 67 SCL SDA A0H 01 2 3 45 67 00H WP VP = 12-15V 01 2 3 45 67 xxH* 0 1 2 3 456 7 00H *for VVTRIP2 address is 0DH for VTRIP address is 01H X40626 |
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