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X55060 Datasheet(PDF) 4 Page - Intersil Corporation

Part No. X55060
Description  Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home

X55060 Datasheet(HTML) 4 Page - Intersil Corporation

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March 28, 2005
Power-On Reset
Application of power to the X55060 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When VCC exceeds the device VTRIP1
value for 150ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low VCC (V1MON) Voltage Monitoring
During operation, the X55060 monitors the VCC level
and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP1. During this time the
communication to the device is interrupted. The
RESET/RESET signal also prevents the microproces-
sor from operating in a power fail or brownout condi-
tion. The RESET signal remains active until the
voltage drops below 1V. These also remain active until
VCC returns and exceeds VTRIP1 for tPURST.
Low V2MON Voltage Monitoring
The X55060 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. V2FAIL remains active until V2MON
returns and exceeds VTRIP2.
The V2MON voltage sensor is powered by VOUT. If
VCC and VBATT go away (i.e. VOUT goes away), then
V2MON cannot be monitored.
Output Voltage. VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1, then,
VOUT = VCC if VCC > VBATT+0.03
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
Battery On. This open drain output goes HIGH when the VOUT switches to VBATT and goes LOW
when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to
the VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
Output/Manual Reset Input. This is an Input/Output pin.
RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls
below the minimum VCC sense level. When RESET is active communication to the device is inter-
rupted. RESET remains active until VCC rises above the minimum VCC sense level for 150ms.
RESET also goes active on power-up and remains active for 150ms after the power supply
MR Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins
are asserted. When MR is released, the RESET/RESET remains asserted for tPURST, and then re-
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and RESET go ACTIVE.

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