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X45620 Datasheet(PDF) 3 Page - Intersil Corporation

Part No. X45620
Description  Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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X45620 Datasheet(HTML) 3 Page - Intersil Corporation

 
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3
FN8250.0
July 29, 2005
8
RESET
/MR
Reset Output/Manual Reset Input. This is an Input/Output pin.
RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls
below the minimum VCC sense level. When RESET is active communication to the device is interrupt-
ed. RESET remains active until VCC rises above the minimum VCC sense level for tPURST. RESET
also goes active on power-up and remains active for tPURST after the power supply stabilizes.
MR Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR is released, the RESET remains asserted for tPURST, and then released.
9WDO
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
10
VSS
Ground
11
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
14
SCL
Serial Clock. The SCL input is used to clock all data into and out of the device.
12–13
NC
No internal connections
15
VBATT
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect VBATT
to ground.
16
VOUT
Output Voltage.
VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1, then,
VOUT = VCC if VCC > VBATT+0.03
VOUT = VBATT if VCC < VBATT-0.03
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
17
BATT-ON
Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW
when VOUT switches to VCC. It is used to drive a external P-channel FET when VCC = VOUT and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the
VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
18
NC
No Connect
19
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down
resistor. (>10M
Ω typical)
20
VCC
(V1MON)
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and LOWLINE go ACTIVE.
PIN DESCRIPTION (Continued)
Pin
Name
Function
X45620


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