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X9430WS24 Datasheet(PDF) 4 Page - Intersil Corporation |
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X9430WS24 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 21 page 4 FN8198.0 March 11, 2005 Potentiometer/Array Description The X9430 is comprised of two resistor arrays and two operational amplifiers. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a volatile wiper counter register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Operational Amplifier The voltage operational amplifiers are CMOS rail-to- rail output general purpose amplifiers. They are designed to operate from dual (±) power supplies. The amplifiers may be configured like any standard ampli- fier. All pins are externally available to allow connec- tion with the potentiometers or as stand alone amplifiers. Write in Process The contents of the data registers are saved to nonvol- atile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write opera- tion can be monitored by a write in process bit (WIP). The WIP bit is read with a read status command. INSTRUCTIONS AND PROGRAMMING Identification (ID) Byte The first byte sent to the X9430 from the host, follow- ing a CS going HIGH to LOW, is called the identifica- tion byte. The most significant four bits of the slave address are a device type identifier, for the X9430 this is fixed as 0101[B] (refer to Figure 1). Detailed Block Diagram VOUT (0,1) (DR0 - DR3)0,1 Control and CS SCK SO SI A1 A0 VH (0,1) VL (0,1) WP VW (0,1) VN (0,1) + – WCR0,1 (DR0 - DR3)0,1 VINV (0,1) VSS VCC HOLD Memory WCR0 WCR1 (One of 2 Circuits) X9430 |
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