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X9111TV14-2.7 Datasheet(PDF) 6 Page - Intersil Corporation |
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X9111TV14-2.7 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 18 page 6 FN8159.1 March 25, 2005 Five of the seven instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – read the current wiper position of the selected pot, • Write Wiper Counter Register – change current wiper position of the selected pot, • Read Data Register – read the contents of the selected data register; • Write Data Register – write a new value to the selected data register. • Read Status – This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 4). Two instructions require a two-byte sequence to complete (see Figure 2). These instructions transfer data between the host and the X9111; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: • XFR Data Register to Wiper Counter Register –This transfers the contents of one specified Data Register to the associated Wiper Counter Register. • XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. See Instruction format for more details. Write in Process (WIP bit) The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command (see Figure 4). Power Up and Down Requirements There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the VCC is always more positive than or equal to the voltages at RH, RL, and RW, i.e., VCC ≥ RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1millisecond after VCC reaches its final value. ID3 ID2 ID1 ID0 0 A1 A0 I2 I1 I0 RB RA SCK SI CS 0101 R/W Device ID Internal Instruction Opcode Address Register 0 0 0 0 Address 0 0 FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE ID3 ID2 ID1 ID0 0 A0R/W I2 00 SCK SI 0 0 X X0 0 XX X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 CS I1 I0 0 RB RA 0 101 0 XX X Device ID Internal Address Instruction Opcode Register Address Wiper Position A1 FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) X9111 |
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