MOTOROLA

MPC555 Product Brief

3

Key Features

1.2.2

U-Bus System Interface Unit (USIU)

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Clock synthesizer

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Power management

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Reset controller

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MPC555 decrementer and time base

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Real-time clock register

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Periodic interrupt timer

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Hardware bus monitor and software watchdog timer

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Interrupt controller that supports up to eight external and eight internal interrupts

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IEEE 1149.1 JTAG test access port

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External bus interface

— 24 address pins, 32 data pins

— Supports multiple master designs

— Four-beat transfer bursts, two-clock minimum bus transactions

— Supports 5V inputs, provides 3.3-V outputs

1.2.3

Flexible Memory Protection Unit

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Four instruction regions and four data regions

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4-Kbyte to 16-Mbyte region size support

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Default attributes available in one global entry

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Attribute support for speculative accesses

1.2.4

448-Kbyte Flash EEPROM Memory

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One 256-Kbyte and one 192-Kbyte module

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Page read mode

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Block (32-Kbyte) erasable

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External 4.75-V to 5.25-V program and erase power supply

1.2.5

26-Kbytes of Static RAM

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One 16-Kbyte and one 10-Kbyte module

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Fast (one-clock) access

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Keep-alive power

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Soft defect detection (SDD)

1.2.6

General-Purpose I/O Support

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Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode

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Nine general-purpose I/O pins in MIOS1 unit

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Many peripheral pins can be used for general-purpose I/O when not used for primary function

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5-V tolerant inputs/outputs