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X4043PZ-2.7A Datasheet(PDF) 5 Page - Intersil Corporation |
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X4043PZ-2.7A Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 24 page 5 FN8118.1 September 30, 2005 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/RESET allowing the system to begin operation. Low Voltage Monitoring During operation, the X4043/45 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the (RESET/RESET) signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor intructions namely, a Start, Clock Low, Clock High and Stop. (See Page 18) The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. Figure 1. Watchdog Restart EEPROM Inadvertent Write Protection When RESET/RESET goes active as a result of a low voltage condition (VCC < VTRIP), any in-progress com- munications are terminated. While VCC < VTRIP, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory block lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VTRIP Programming The X4043/45 is shipped with a standard VCC thresh- old (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4043/45 threshold may be adjusted. The procedure is described below, and uses the applica- tion of a high voltage control signal. Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set) SCL SDA .6µs 1.3µs Start Stop Reset WDT 01 2 3 4 5 67 SCL SDA A0h 01 2 3 4 5 67 01h WP VP = 15-18V 01 2 3 4 5 67 00h X4043, X4045 |
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