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X28C513JM-15 Datasheet(PDF) 5 Page - Intersil Corporation |
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X28C513JM-15 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 25 page 5 FN8106.1 September 29, 2005 Pinouts Pin Descriptions Addresses (A0-A15) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C512, X28C513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C512, X28C513. NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O5 I/O4 I/O3 I/O2 I/O1 X28C512 Plastic DIP CERDIP FLAT Pack SOIC (R) Bottom 14 A0 16 I/O 1 18 VSS 11 A3 9 A5 7 A7 15 I/O0 17 I/O 2 19 I/O 3 5 A15 2 NC 36 VCC 20 I/O 4 21 I/O 5 34 NC 23 I/O 7 25 A10 27 A11 29 A8 22 I/O 6 32 NC 24 CE 26 OE 28 A9 30 A13 13 A1 12 A2 10 A4 8 A6 4 NC 3 NC 1 NC 35 WE 33 NC 31 A14 6 A12 PGA X28C512 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A13 A8 A9 A11 OE A10 CE I/O7 A14 2 32 6 1 5 4 3 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 14 21 30 PLCC/LCC X28C513 A6 A5 A4 A3 A2 A1 A0 NC I/O0 A9 A11 NC OE A10 CE I/O6 A8 2 32 6 1 5 4 3 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 14 21 30 I/O7 View (Top View) (Top View) Pin Names SYMBOL DESCRIPTION A0-A15 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect X28C512, X28C513 |
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