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X1243 Datasheet(PDF) 9 Page - Intersil Corporation

Part No. X1243
Description  Real Time Clock/Calendar/Alarm with EEPROM
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X1243 Datasheet(HTML) 9 Page - Intersil Corporation

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9
FN8249.0
April 28, 2005
Page Write
The X1243 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the rst data byte is
transferred, the master can transmit up to 63 more bytes to
the memory array and up to 7 more bytes to the clock/control
registers.
(Note: Prior to writing to the CCR, the master must write a
02h, then 06h to the status register in two pre-ceding
operations to enable the write operation. See “Writing to the
Clock/Control Registers” on page 6.)
After the receipt of each byte, the X1243 responds with an
acknowledge, and the address is internally incre-mented by
one. When the counter reaches the end of the page, it “rolls
over” and goes back to the rst address on the same page.
This means that the mas-ter can write 64-bytes to a memory
array page or 8-bytes to a CCR section starting at any
location on that page. If the master begins writing at location
40 of the memory and loads 30 bytes, then the rst 23-bytes
are written to addresses 40 through 63, and the last 7-bytes
are written to columns 0 through 6. Afterwards, the address
counter would point to location 7 on the page that was just
written. If the master supplies more than the maximum bytes
in a page, then the previously loaded data is over written by
the new data, one byte at a time.
The master terminates the Data Byte loading by issu-ing a
stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write oper-ation, all
inputs are disabled until completion of the internal write
cycle. Refer to Figure 8 for the address, acknowledge, and
data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be affected.
Acknowledge Polling
The disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the device initiates the
internal nonvolatile write cycle. Acknowledge polling can be
initiated immediately. To do this, the master issues a start
condition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the nonvolatile
write cycle then no ACK will be returned. If the device has
com-pleted the write operation, an ACK will be returned and
the host can then proceed with the read or write opera-tion.
Refer to the ow chart in Table 9.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-mented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power up, the sixteen bit address is initialized to 0h. In this
way, a current address read can be initiated immediately
after the power on reset to download the contents of memory
starting at the rst location.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The mas-ter
terminates the read operation when it does not respond with
an acknowledge during the ninth clock and then issues a
stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
ACK
Returned?
Issue Slave
Address Byte
(Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Issue STOP
NO
Continue Normal
Read or Write
Command
Sequence
PROCEED
YES
Nonvolatile Write
Cycle Complete.
Continue Command
Sequence?
FIGURE 9. ACKNOWLEDGE POLLING SEQUENCE
X1243


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