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ISL6424 Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6424 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 12 page 8 FN9175.3 September 13, 2005 When the ENT1/2 bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN1/2 pin logic status for the corresponding regulator channel (LNB-A or LNB-B). The ENT1/2 bit must be set LOW when the DSQIN1 and/or DSQIN2 pin is used for DiSEqC encoding. Linear Regulator The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25 µF. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN1, EN2 = LOW), both PWM power blocks are disabled. (i.e. when EN1 = 0, PWM1 is disabled, and when EN2 = 0, PWM2 is disabled). When the regulator blocks are active (EN1, EN2 = HIGH), the output can be logic controlled to be 13V or 18V (typical) by means of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC1/2 bit HIGH). Output Timing The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47 µF to 2.2µF, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47 µF capacitor insures the PWM stays below its overcurrent threshold when charging a 120 µF VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0 µF is recommended. This feature only affects the turn-on and programmed voltage rise and fall times. Current Limiting The current limiting block has two thresholds that can be selected by the ISEL bit of the SR and can work either statically (simple current clamp) or dynamically. The lower threshold is between 425mA and 550mA (ISEL = L), while the higher threshold is between 775mA and 950mA (ISEL = H). When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shutdown for a time tOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time tON = 20ms. During tON, the device output will be current limited to 425mA min. or 775mA min., depending on the ISEL bits. At the end of tON, if the overload is still detected, the protection circuit will cycle again through tOFF and tON. At the end of a full tON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical tON + tOFF time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF1/2 bit goes HIGH when the current limit threshold at the CS pin reaches 0.45V typ and returns LOW when the overload condition is cleared. The OLF1/2 bit will be LOW at the end of initial power-on soft-start. Thermal Protection This IC is protected against overheating. When the junction temperature exceeds 150°C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW when the junction is cooled down to 135°C (typical). In over temperature conditions, the OTF Flag goes HIGH and the I2C data will be cleared. The user may need to monitor the I2C enable bits and OTF flag continuously and enable the chip, if I2C data is cleared. OTF conditions may also make the OLF flags go HIGH, when high capacitive loads are present or self-heating conditions occur at higher loads. External Output Voltage Selection The output voltage can be selected by the I2C bus. Additionally, the package offers two pins (SEL18V1, SEL18V2) for independent 13V/18V output voltage selection. When using these pins, the I2C bits should be initialized to 13V status. I2C Bus Interface for ISL6424 (Refer to Philips I2C Specification, Rev. 2.1) Data transmission from main microprocessor to the ISL6424 and vice versa takes place through the two wire I2C bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stages of ISL6424 will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100Kbps TABLE 1. I2C BITS SEL18V (1, 2) O/P VOLTAGE 13V Low 13V 14V Low 14V 13V High 18V 14V High 18V ISL6424 |
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