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M5M5V216ATP Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part No. M5M5V216ATP
Description  2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M5V216ATP Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI ELECTRIC
M5M5V216ATP,RT
revision-01, ' 98.12.08
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
FUNCTION TABLE
2
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by
16-bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S. The address(A0~A16) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S are in
an active state(S=L).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
When setting BC1 and BC2 at a high level or S at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3µA(25 C,
typical), and the memory data can be held
at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
BLOCK DIAGRAM
Mode
S
W
H
X
X
High-Z
S BC1 BC2
OE
DQ1~8
X
X
Non selection
DQ9~16
Icc
High-Z Standby
High-Z High-Z
L
X
L
L
H
Din
High-Z
Active
L
H
L
H
Read
High-Z
Dout
Active
L
L
H
L
Active
L
H
L
Active
L
L
High-Z
High-Z
Active
H
L
H
H
High-Z
L
L
Dout
H
L
L
Read
Dout
Active
L
L
Din
L
L
X
Write
Din
Active
H
High-Z
H
H
High-Z High-Z
Non selection
H
H
X
X
Standby
Write
L
H
L
L
Write
Din
Active
X
L
L
H
Read
High-Z
Active
L
Dout
H
High-Z
MEMORY ARRAY
131072 WORDS
x 16 BITS
CLOCK
GENERATOR
A0
A1
A15
A16
S
BC1
BC2
W
OE
DQ
8
DQ
1
DQ
16
DQ
9
-
Vcc
GND
L


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