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M5M5V208FP-70L Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part No. M5M5V208FP-70L
Description  2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M5M5V208FP-70L Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

   
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MITSUBISHI LSIs
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
'97.3.21
FUNCTION
FUNCTION TABLE
DQ1
DQ2
DQ3
DQ4
VCC
(3V)
GND
(0V)
W
OE
DQ5
DQ6
DQ7
DQ8
BLOCK DIAGRAM
24
13
14
15
17
32
16
S1
22
18
19
20
21
29
262144 WORDS
X 8 BITS
512 ROWS
X 128 COLUMNS
X
32 BLOCKS
CLOCK
GENERATOR
8
A4
7
A5
6
A6
5
A7
4
A12
3
A14
2
A16
1
A17
31
A15
12
A0
11
A1
10
A2
23
A10
25
A11
26
A9
27
A8
28
A13
A read cycle is executed by setting W at a high level and
OE at a low level while S1 and S2 are in an active state (S1
= L ,S2 = H).
When setting S1 at a high level or S2 at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S1 or S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
The operation mode of the M5M5V208 is determined by a
combination of the device control inputs S1, S 2, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
Mode
DQ
Icc
S1
W
OE
Non selection
Write
Read
High-impedance
Standby
Active
Active
Active
High-impedance
D IN
D OUT
H
X
X
L
L
L
L
H
H
X
L
H
S2
L
X
H
X
H
H
X
X
Non selection
High-impedance
Standby
9
A3
S2
30
31
1
2
3
4
20
19
18
17
16
15
14
13
12
11
10
9
7
32
8
24
30
5
6
21
22
23
25
26
27
28
29
*
*
*Pin numbers inside dotted line show those of TSOP.
2


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