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AD5258 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD5258
Description  Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer
Download  24 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5258 Datasheet(HTML) 5 Page - Analog Devices

 
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AD5258
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time between STOP and START
t1
1.3
µs
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock pulse is
generated.
0.6
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Setup Time for Repeated START
Condition
t5
0.6
µs
tHD;DAT Data Hold Time
t6
0
0.9
µs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for STOP Condition
t10
0.6
µs
EEPROM Data Storing Time
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at Power On1
tEEMEM_RESTORE1
VDD rise time dependant. Measure
without decoupling capacitors at VDD and
GND.
300
µs
EEPROM Data Restoring Time upon Restore
Command1
tEEMEM_RESTORE2
VDD = 5 V.
300
µs
EEPROM Data Rewritable Time2
tEEMEM_REWRITE
540
µs
FLASH/EE MEMORY RELIABILITY
Endurance3
100
700
kCycles
Data Retention4
100
Years
1 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2 Delay time after power-on PRESET prior to writing new EEPROM data.
3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
t1
SCL
SDA
PS
P
t3
t2
t8
t9
t8
t9
t4
t5
t7
t6
t10
Figure 4. I2C Interface Timing Diagram


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