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TP3054-X Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TP3054-X
Description  Extended Temperature Serial Interface CODEC/Filter COMBO Family
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

TP3054-X Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Functional Description (Continued)
To use the long frame mode, both the frame sync pulses,
X and FSR, must be three or more bit clock periods long,
with timing relationships specified in Figure 3. Based on the
transmit frame sync, FS
X, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The D
X TRI-STATE output buffer is
enabled with the rising edge of FS
X or the rising edge of
X, whichever comes later, and the first bit clocked out
is the sign bit. The following seven BCLK
X rising edges clock
out the remaining seven bits. The D
X output is disabled by
the falling BCLK
X edge following the eighth rising edge, or by
X going low, whichever comes later. A rising edge on the
receive frame sync pulse, FS
R, will cause the PCM data at
R to be latched in on the next eight falling edges of BCLKR
X in synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
In applications where the LSB bit is used for signalling, with
R two bit clock periods long, the decoder will interpret the
lost LSB as “12” to minimize noise and distortion.
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized.
The op amp drives a unity-gain filter consisting of RC active
pre-filter, followed by an eighth order switched-capacitor
bandpass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. The A/D
is of companding type according to µ-law (TP3054) or A-law
(TP3057) coding conventions. A precision voltage reference
is trimmed in manufacturing to provide an input overload
MAX) of nominally 2.5V peak (see table of Transmission
Characteristics). The FS
X frame sync pulse controls the
sampling of the filter output, and then the successive-
approximation encoding cycle begins. The 8-bit code is then
loaded into a buffer and shifted out through D
X at the next
X pulse. The total encoding delay will be approximately
165 µs (due to the transmit filter) plus 125 µs (due to encod-
ing delay), which totals 290 µs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter clocked
at 256 kHz. The decoder is A-law (TP3057) or µ-law
(TP3054) and the 5th order low pass filter corrects for the sin
x/x attenuation due to the 8 kHz sample/hold. The filter is
then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 600
Ω load to a level of 7.2
dBm. The receive section is unity-gain. Upon the occurrence
of FS
R, the data at the DR input is clocked in on the falling
edge of the next eight BCLK
R (BCLKX) periods. At the end of
the decoder time slot, the decoding cycle begins, and 10 µs
later the decoder DAC output is updated. The total decoder
delay is
∼10 µs (decoder update) plus 110 µs (filter delay)
plus 62.5 µs (12 frame), which gives approximately 180 µs.

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