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TP3054-X Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. TP3054-X
Description  Extended Temperature Serial Interface CODEC/Filter COMBO Family
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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TP3054-X Datasheet(HTML) 2 Page - National Semiconductor (TI)

 
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Pin Descriptions
Symbol
Function
V
BB
Negative power supply pin.
V
BB = −5V ±5%.
GNDA
Analog ground. All signals are
referenced to this pin.
VF
RO
Analog output of the receive power
amplifier.
V
CC
Positive power supply pin.
V
CC = +5V ±5%.
FS
R
Receive frame sync pulse which
enables BCLK
R to shift PCM data into
D
R.FSR is an 8 kHz pulse train. See
Figure 2 and Figure 3 for timing details.
D
R
Receive data input. PCM data is shifted
into D
R following the FSR leading edge.
Symbol
Function
BCLK
R/CLKSEL The bit clock which shifts data into DR
after the FS
R leading edge. May vary
from 64 kHz to 2.048 MHz.
Alternatively, may be a logic input
which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in
synchronous mode and BCLK
X is used
for both transmit and receive directions
(see Table 1).
MCLK
R/PDN
Receive master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
X, but should
be synchronous with MCLK
X for best
performance. When MCLK
R is
connected continuously low, MCLK
X is
selected for all internal timing. When
MCLK
R is connected continuously high,
the device is powered down.
Block Diagram
00867402
FIGURE 1.
www.national.com
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