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CS44600-CQZ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS44600-CQZ Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 78 page DS633PP1 7 CS44600 LIST OF TABLES Table 1. Common DAI_MCLK Frequencies.................................................................................. 24 Table 2. DAI Serial Audio Port Channel Allocations ..................................................................... 26 Table 3. Load Compensation Example Settings ........................................................................... 31 Table 4. Typical PWM Switch Rate Settings................................................................................. 33 Table 5. Digital Audio Interface Formats....................................................................................... 51 Table 6. Master Integer Volume Settings...................................................................................... 55 Table 7. Master Fractional Volume Settings ................................................................................. 56 Table 8. Channel Integer Volume Settings ................................................................................... 57 Table 9. Channel Fractional Volume Settings............................................................................... 58 Table 10. Limiter Attack Rate Settings..........................................................................................60 Table 11. Limiter Release Rate Settings....................................................................................... 60 Table 12. Channel Load Compensation Filter Coarse Adjust ....................................................... 61 Table 13. Channel Load Compensation Filter Fine Adjust............................................................ 61 Table 14. PWM Minimum Pulse Width Settings............................................................................ 68 Table 15. Differential Signal Delay Settings.................................................................................. 68 Table 16. Channel Delay Settings................................................................................................. 68 Table 17. Power Supply Sync Clock Divider Settings................................................................... 70 Table 18. Decimator Shift/Scale Coefficient Calculation Examples .............................................. 71 Table 19. Revision History ............................................................................................................ 77 |
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