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TP5208P Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part # TP5208P
Description  64K SRAM ECHO PROCESSOR
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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TP5208P Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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TP5208
64K SRAM ECHO PROCESSOR
Data Sheet - Version 1.1
Page 3 of 7
http://www.topro.com.tw
January 2005
U-COM Mode (EASY/U-COM = L)
H
Delay Time
H
ID Code
= SLEEP Mode
= MUTE
This timing chart shows that delay time is set by serial data from U-COM.
DATA signal is latched at the falling edge of
SCK signal; the last ten data are set at the rising edge of REQ signal when ID codes are satisfied.
ID1, ID3: L
ID2: H
ID4: equal to IDSW
REQ, SCK, DATA Input Timing
Limit
Symbol
Parameter
Min
Typ
Max
Unit
t1
SCK Pulse Width
250
-
-
ns
ds
SCK Pulse Duty
-
50
-
%
t2
DATA Setup Time
100
t1/2
-
ns
t3
DATA Hold Time
100
t1/2
-
ns
t4
REQ Hold Time
100
-
-
ns
t5
REQ Pulse Width
250
-
-
ns
MUTING
EASY mode
Automatic mute upon changing delay time, canceling SLEEP mode and power-on.
U-COM mode
MUTE = H: mute
MUTE = L: automatic mute


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