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CS4922 Datasheet(PDF) 10 Page - Cirrus Logic

Part # CS4922
Description  MPEG/G.729A AUDIO DECODER SYSTEM
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4922 Datasheet(HTML) 10 Page - Cirrus Logic

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CS4922
10
SWITCHING CHARACTERISTICS - CONTROL PORT (I2C MODE) (T
A = 25 °C;
VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF)
Notes: 10. Use of I2C® bus compatible interface requires a license from Philips.
11. Data must be held for sufficient time to bridge the 300ns transition time of SCK/SCL.
12. This rise time is shorter than the I2C specifications recommend, please refer to the section on SCP
communications for more information.
13. REQ will only go HIGH if there is no data in the SCPOUT register at the rising edge of SCL/SCK during
a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 k
Ω C
L = 20pF.
14. if REQ went HIGH as indicated in Note 13 then REQ will hold HIGH at least until the next rising edge of
SCK/SCL. If data is in the SCPOUT register at this time REQ will go active LOW again. This condition
should be treated as a new READ process. The address and R/W should be sent again following a new
START condition.
Parameter
Symbol
Min
Max
Units
I2C® Mode (CS=1)
(Note 10)
SCK/SCL Clock Frequency
(slow mode)
(fast mode)
fscl
100
400
kHz
Bus Free Time Between Transmissions
tbuf
4.7
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
µs
Clock Low Time
slow
fast
tlow
4.7
1.2
µs
Clock High Time
slow
fast
thigh
4.0
1.0
µs
SDA Setup Time to SCK/SCL Rising
tsud
250
ns
SDA Hold Time from SCK/SCL Falling
(Note 11)
thdd
0
µs
Rise Time of Both SDA and SCK/SCL
(Note 12)
tr
50
ns
Fall Time of Both SDA and SCK/SCL
tf
300
ns
Time from SCK/SCL Falling to CS4920 ACK
tsca
40
ns
Time from SCK/SCL Falling to SDA
Valid During READ Operation
tscsdv
40
ns
Time from SCK/SCL Rising to REQ Rising
(Note 13)
tscrh
200
ns
Hold Time for REQ from SCK/SCL Rising
(Note 14)
tscrl
0ns
Rise Time for REQ
(Note 13)
trr
50
ns
Fall Time for REQ
(Note 14)
trf
20
ns
Setup Time for Stop Condition
tsusp
4.7
µs


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