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MC14504B Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC14504B
Description  Hex Level Shifter for TTL to CMOS or COMS to CMOS
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC14504B Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14504B/D
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non–inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The
VCC level sets the input signal levels while VDD selects the output
voltage levels.
UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for V
DD and VCC
Diode Protected Inputs to V
SS
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage Range
– 0.5 to +18.0
V
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin
Input Voltage Range
(DC or Transient)
– 0.5 to +18.0
V
Vout
Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14504BCP
PDIP–16
2000/Box
MC14504BD
SOIC–16
48/Rail
MC14504BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14504BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14504B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14504B
AWLYWW
MC14504BF
SOEIAJ–16
See Note 1.
MC14504BFEL
SOEIAJ–16
See Note 1.
MC14504BDT
TSSOP–16
96/Rail
TSSOP–16
DT SUFFIX
CASE 948F
14
504B
ALYW
1
16


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