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TM2SN64EPN Datasheet(PDF) 7 Page - Texas Instruments |
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TM2SN64EPN Datasheet(HTML) 7 Page - Texas Instruments |
7 / 16 page TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS696 – AUGUST 1997 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3) TM2SN64EPN PARAMETER TEST CONDITIONS ’2SN64EPN-10 ’2SN64EPN-12 UNIT PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 2 mA 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 V II Input current (leakage) 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD "10 "10 µA IO Output current (leakage) 0 V < VO < VDD +0.3 V, Output disabled "10 "10 µA ICC1 Operating current Burst length = 1, tRC ≥ tRC MIN CAS latency = 2 760 720 mA ICC1 Operating current RC RC IOH/IOL = 0 mA, one bank activated (see Note 4) CAS latency = 3 840 720 mA ICC2P Precharge standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 16 16 mA ICC2PS gy power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 16 16 mA ICC2N Precharge standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 200 200 mA ICC2NS Precharge standby current in non-power-down mode CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 16 16 mA ICC3P Active standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 24 24 mA ICC3PS y power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 24 24 mA ICC3N Active standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 240 240 mA ICC3NS Active standby current in non-power-down mode CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 80 80 mA ICC4 Burst current Page burst, IOH/IOL = 0 mA All banks activated, CAS latency = 2 800 760 mA ICC4 Burst current , nCCD = one cycle (see Note 7) CAS latency = 3 1040 1000 mA ICC5 Auto refresh current tRC ≤ tRC MIN CAS latency = 2 680 640 mA ICC5 Auto-refresh current tRC ≤ tRC MIN CAS latency = 3 760 640 mA ICC6 Self-refresh current CKE ≤ VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state twice during tRC. 5. Control, DQ, and address inputs change state once every 30 ns. 6. Control, DQ, and address inputs do not change. 7. Control, DQ, and address inputs change once every cycle. |
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