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MC14093B Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC14093B
Description  Quad 2-Input NAND Schmitt Trigger
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC14093B Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14093B/D
MC14093B
Quad 2-Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2–input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt–Trigger at each Input
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14093BCP
PDIP–14
2000/Box
MC14093BD
SOIC–14
2750/Box
MC14093BDR2
SOIC–14
2500/Tape & Reel
MC14093BDT
TSSOP–14
MC14093BF
SOEIAJ–14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC14093BCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
14093B
AWLYWW
14
093B
ALYW
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14093B
AWLYWW
MC14093BFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14093BDTR2
TSSOP–14 2500/Tape & Reel
MC14093BDTEL
TSSOP–14 2000/Tape & Reel


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