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LTC2439-1 Datasheet(PDF) 23 Page - Linear Technology

Part # LTC2439-1
Description  8-/16-Channel 16-Bit No Latency Delta-Sigma ADC
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2439-1 Datasheet(HTML) 23 Page - Linear Technology

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LTC2439-1
23
24391f
and each ohm of source resistance driving IN+ or INwill
result in 1.11 • 10–7 • fEOSCLSB gain error at full scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN+ and INfor large values of CIN are shown
in Figures 16 and 17.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and INand with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN+ and INpins. When FO = LOW
(internal oscillator and 50Hz/60Hz notch), every 60
Ω mis-
match in source impedance transforms a full-scale com-
mon mode input signal into a differential mode input
signal of 1LSB. When FO is driven by an external oscillator
with a frequency fEOSC, every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 1.11 • 10–7
• fEOSCLSB. Figure 18 shows the typical offset error due to
input common mode voltage for various values of source
resistance imbalance between the IN+ and INpins when
large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
RSOURCE (Ω)
0 100 200 300 400 500 600 700 800 900 1000
24361 F16
20
16
12
8
4
0
VCC = 5V
REF+ = 5V
REF = GND
IN+ = 3.75V
IN= 1.25V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.1µF
CIN = 1µF, 10µF
RSOURCE (Ω)
0 100 200 300 400 500 600 700 800 900 1000
24361 F17
0
–4
–8
–12
–16
–20
VCC = 5V
REF+ = 5V
REF = GND
IN+ = 1.25V
IN= 3.75V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0.1µF
CIN = 1µF, 10µF
VINCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
24361 F18
8
4
0
–4
–8
FO = GND
TA = 25°C
RSOURCEIN– = 500Ω
CIN = 10µF
VCC = 5V
REF+ = 5V
REF = GND
IN+ = IN= VINCM
A:
∆RIN = +400Ω
B:
∆RIN = +200Ω
C:
∆RIN = +100Ω
D:
∆RIN = 0Ω
E:
∆RIN = –100Ω
F:
∆RIN = –200Ω
G:
∆RIN = –400Ω
A
B
C
D
E
F
G
Figure 16. +FS Error vs RSOURCE at IN+ or IN(Large CIN)
Figure 17. –FS Error vs RSOURCE at IN+ or IN(Large CIN)
Figure 18. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN) and Input Source Resistance
Imbalance (
∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
APPLICATIO S I FOR ATIO


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