(Bit 18) for the next conversion cycle. Table 3 summarizes
the output data format.
In order to remain compatible with some SPI
microcontrollers, more than 19 SCK clock pulses may be
applied. As long as these clock pulses are complete before
the conversion ends, they will not effect the serial data.
However, switching SCK during a conversion may gener-
ate ground currents in the device leading to extra offset
and noise error sources.
As long as the voltage applied to any channel (CH0-CH15,
COM) is maintained within the – 0.3V to (VCC + 0.3V)
absolute maximum operating range, a conversion result is
generated for any differential input voltage VIN from
–FS = – 0.5 • VREF to +FS = 0.5 • VREF. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For differ-
ential input voltages below –FS, the conversion result is
clamped to the value corresponding to –FS – 1LSB.
Simultaneous Frequency Rejection
The LTC2439-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz as shown in Figure 4. For simultaneous 50Hz/60Hz
rejection using the internal oscillator, FO should be con-
nected to GND.
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be sychronized with an outside source, the LTC2439-1
APPLICATIO S I FOR ATIO
can operate with an external conversion clock. The conveter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods, tHEO and tLEO,
While operating with an external conversion clock of a
normal mode rejection in a frequency range fEOSC/2560
±4%. The normal mode rejection as a function of the input
frequency deviation from fEOSC/2560 is shown in Figure 5.
Whenever an external clock is not present at the FO pin the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2439-1
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the data
output state while the converter uses an external serial clock.
If the change occurs during the conversion state, the result
of the conversion in progress may be outside specifications
but the following conversions will not be affected. If the
change occurs during the data output state and the con-
verter is in the Internal SCK mode, the serial clock duty cycle
may be affected but the serial data stream will remain valid.
Table 4 summarizes the duration of each state and the
achievable output data rate as a function of FO.
Figure 4. LTC2439-1 Normal Mode Rejection
When Using an Internal Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
Figure 5. LTC2439-1 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)