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M5M5V108CFP-70H Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part No. M5M5V108CFP-70H
Description  1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M5V108CFP-70H Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
M5M5V108CFP,VP,RV,KV,KR -70H, -10H,
-70X, -10X
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
MITSUBISHI
ELECTRIC
FUNCTION
BLOCK DIAGRAM
The operation mode of the M5M5V108C series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S 1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or S2,
whichever occurs first,requiring the set-up and hold time relative to
these edge to be maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level, the output
stage is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
When setting S1 at a high level or S2 at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
S1
S2
W
OE
Mode
DQ
ICC
L
L
H
H
H
H
L
H
Non selection
Write
Read
High-impedance
Din
Dout
Active
Stand-by
Non selection High-impedance
High-impedance
Active
Active
Stand-by
FUNCTION TABLE
L
H
L
X
H
X
X
X
X
L
X
X
2
CLOCK
GENERATOR
131072 WORDS
X 8 BITS
( 512 ROWS
X128 COLUMNS
X 16BLOCKS )
8
7
6
5
4
3
2
31
28
16
15
14
13
12
11
10
7
4
12
11
10
9
20
19
18
17
27
26
25
3
2
1
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
5
30
6
32
8
29
22
30
24
32
16
24
A4
A5
A6
A7
A12
A14
A16
A15
A13
A0
A1
A2
A3
A8
A9
A11
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
W
S1
S2
OE
VCC
GND
(0V)
* Pin numbers inside dotted line show those of TSOP
*
*
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
CHIP
SELECT
INPUTS
OUTPUT
ENABLE
INPUT
ADDRESS
INPUTS
23
31
A10


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