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MT90401 Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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MT90401 Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 38 page  MT90401 Data Sheet 5 Zarlink Semiconductor Inc. 45 VSS5 Digital ground. 0 Volts 46 C19o Clock 19.44 MHz (CMOS Output). This output is used in OC-N and STM-N applications. 47 RSEL Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. The logic level at this input is gated in by the rising edge of F8o. For more details see RSEL bit description in Table 6 - Control Register 1 (Address 00H - Read/Write). 48 TCLR TIE Circuit Clear (Input). A logic low at this input clears the Time Interval Error (TIE) correction circuit resulting in a realignment of output phase with input phase. The TCLR pin should be held low for a minimum of 300 ns. When this pin is held low, the time interval error correction circuit is disabled. 49 VDD3 Positive Power Supply. Digital supply. 50 NC No Connection. 51 C20i 20 MHz Clock Input (5 V tolerant Input). This pin is the input for the master 20 MHz clock. 52 VSS7 Digital ground. 0Volts 53 C34/C44 Controlled Clock 34.368 MHz / Clock 44.736 MHz (CMOS Output). This output clock is programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3 applications). The output clock is controlled via control pins in Hardware Mode or control bits when the device is in Microport Mode. If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal frequency divided by 4. (C8.5o/C11o) 54 VDD4 Positive Power Supply. Digital supply. 55 HOLDOVER Holdover (CMOS Output). This output goes high when the device is in holdover mode. 56 PCCi Phase Continuity Control Input (3 V Input). The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge of F8o. See Figure 12, “Control State Diagram” on page 21 for details. 57 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is in frequency lock to the input reference. 58 FLOCK Fast Lock Mode (Input). In hardware mode, hold this pin high to lock faster than normal to the input reference. This pin performs no function if the device is not in hardware mode. In Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised. 59 DS Data Strobe (5 V tolerant Input). This input is the active low data strobe of the Motorola processor interface. 60 IC Internal Connection. Tie low for normal operation. 61 SECOOR Secondary Reference Out Of Capture Range (CMOS Output). A logic high at this pin indicates that the secondary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20 MHz clock input on the C20i pin. When the accuracy of the 20 MHz clock is ± 4.6 ppm the effective out of range limits of the SECOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Pin Description (continued) Pin # Name Description |
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