5/11

L5970AD

Figure 5. Internal Regulator Circuit

3.3 OSCILLATOR & SYNCHRONIZATOR

Figure 6 shows the block diagram of the oscillator circuit.

The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency

shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is

then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks.

The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal volt-

age feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a

synchronization pin that can works both as Master and Slave.

As Master to synchronize external devices to the internal switching frequency.

As Slave to synchronize itself by external signal.

In particular, connecting together two devices, the one with the lower switching frequency works as Slave and

the other one works as Master.

To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization

threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequen-

cy and amplitude.

The frequency of the synchronization signal must be at least higher than the internal switching frequency of the

device (500KHz).

Figure 6. Oscillator Circuit

STARTER

IC BIAS

PREREGULATOR

BANDGAP

VREG

VREF

D00IN1126

FREQUENCY

SHIFTER

CLOCK

GENERATOR

RAMP

GENERATOR

SYNCHRONIZATOR

CLOCK

RAMP

Ibias_osc

SYNC

t

D00IN1131